
circure-queue:     file format elf64-littleaarch64


Disassembly of section .init:

0000000000400628 <_init>:
  400628:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  40062c:	910003fd 	mov	x29, sp
  400630:	9400004a 	bl	400758 <call_weak_fn>
  400634:	a8c17bfd 	ldp	x29, x30, [sp], #16
  400638:	d65f03c0 	ret

Disassembly of section .plt:

0000000000400640 <.plt>:
  400640:	a9bf7bf0 	stp	x16, x30, [sp, #-16]!
  400644:	b0000090 	adrp	x16, 411000 <__FRAME_END__+0xfe78>
  400648:	f947fe11 	ldr	x17, [x16, #4088]
  40064c:	913fe210 	add	x16, x16, #0xff8
  400650:	d61f0220 	br	x17
  400654:	d503201f 	nop
  400658:	d503201f 	nop
  40065c:	d503201f 	nop

0000000000400660 <memcpy@plt>:
  400660:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400664:	f9400211 	ldr	x17, [x16]
  400668:	91000210 	add	x16, x16, #0x0
  40066c:	d61f0220 	br	x17

0000000000400670 <strlen@plt>:
  400670:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400674:	f9400611 	ldr	x17, [x16, #8]
  400678:	91002210 	add	x16, x16, #0x8
  40067c:	d61f0220 	br	x17

0000000000400680 <exit@plt>:
  400680:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400684:	f9400a11 	ldr	x17, [x16, #16]
  400688:	91004210 	add	x16, x16, #0x10
  40068c:	d61f0220 	br	x17

0000000000400690 <malloc@plt>:
  400690:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400694:	f9400e11 	ldr	x17, [x16, #24]
  400698:	91006210 	add	x16, x16, #0x18
  40069c:	d61f0220 	br	x17

00000000004006a0 <__libc_start_main@plt>:
  4006a0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006a4:	f9401211 	ldr	x17, [x16, #32]
  4006a8:	91008210 	add	x16, x16, #0x20
  4006ac:	d61f0220 	br	x17

00000000004006b0 <memset@plt>:
  4006b0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006b4:	f9401611 	ldr	x17, [x16, #40]
  4006b8:	9100a210 	add	x16, x16, #0x28
  4006bc:	d61f0220 	br	x17

00000000004006c0 <__gmon_start__@plt>:
  4006c0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006c4:	f9401a11 	ldr	x17, [x16, #48]
  4006c8:	9100c210 	add	x16, x16, #0x30
  4006cc:	d61f0220 	br	x17

00000000004006d0 <abort@plt>:
  4006d0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006d4:	f9401e11 	ldr	x17, [x16, #56]
  4006d8:	9100e210 	add	x16, x16, #0x38
  4006dc:	d61f0220 	br	x17

00000000004006e0 <puts@plt>:
  4006e0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006e4:	f9402211 	ldr	x17, [x16, #64]
  4006e8:	91010210 	add	x16, x16, #0x40
  4006ec:	d61f0220 	br	x17

00000000004006f0 <free@plt>:
  4006f0:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  4006f4:	f9402611 	ldr	x17, [x16, #72]
  4006f8:	91012210 	add	x16, x16, #0x48
  4006fc:	d61f0220 	br	x17

0000000000400700 <printf@plt>:
  400700:	d0000090 	adrp	x16, 412000 <memcpy@GLIBC_2.17>
  400704:	f9402a11 	ldr	x17, [x16, #80]
  400708:	91014210 	add	x16, x16, #0x50
  40070c:	d61f0220 	br	x17

Disassembly of section .text:

0000000000400710 <_start>:
  400710:	d280001d 	mov	x29, #0x0                   	// #0
  400714:	d280001e 	mov	x30, #0x0                   	// #0
  400718:	aa0003e5 	mov	x5, x0
  40071c:	f94003e1 	ldr	x1, [sp]
  400720:	910023e2 	add	x2, sp, #0x8
  400724:	910003e6 	mov	x6, sp
  400728:	580000c0 	ldr	x0, 400740 <_start+0x30>
  40072c:	580000e3 	ldr	x3, 400748 <_start+0x38>
  400730:	58000104 	ldr	x4, 400750 <_start+0x40>
  400734:	97ffffdb 	bl	4006a0 <__libc_start_main@plt>
  400738:	97ffffe6 	bl	4006d0 <abort@plt>
  40073c:	00000000 	.inst	0x00000000 ; undefined
  400740:	00400dd0 	.word	0x00400dd0
  400744:	00000000 	.word	0x00000000
  400748:	00400fc8 	.word	0x00400fc8
  40074c:	00000000 	.word	0x00000000
  400750:	00401048 	.word	0x00401048
  400754:	00000000 	.word	0x00000000

0000000000400758 <call_weak_fn>:
  400758:	b0000080 	adrp	x0, 411000 <__FRAME_END__+0xfe78>
  40075c:	f947f000 	ldr	x0, [x0, #4064]
  400760:	b4000040 	cbz	x0, 400768 <call_weak_fn+0x10>
  400764:	17ffffd7 	b	4006c0 <__gmon_start__@plt>
  400768:	d65f03c0 	ret
  40076c:	00000000 	.inst	0x00000000 ; undefined

0000000000400770 <deregister_tm_clones>:
  400770:	d0000080 	adrp	x0, 412000 <memcpy@GLIBC_2.17>
  400774:	9101a000 	add	x0, x0, #0x68
  400778:	d0000081 	adrp	x1, 412000 <memcpy@GLIBC_2.17>
  40077c:	9101a021 	add	x1, x1, #0x68
  400780:	eb00003f 	cmp	x1, x0
  400784:	540000a0 	b.eq	400798 <deregister_tm_clones+0x28>  // b.none
  400788:	b0000001 	adrp	x1, 401000 <__libc_csu_init+0x38>
  40078c:	f9403421 	ldr	x1, [x1, #104]
  400790:	b4000041 	cbz	x1, 400798 <deregister_tm_clones+0x28>
  400794:	d61f0020 	br	x1
  400798:	d65f03c0 	ret
  40079c:	d503201f 	nop

00000000004007a0 <register_tm_clones>:
  4007a0:	d0000080 	adrp	x0, 412000 <memcpy@GLIBC_2.17>
  4007a4:	9101a000 	add	x0, x0, #0x68
  4007a8:	d0000081 	adrp	x1, 412000 <memcpy@GLIBC_2.17>
  4007ac:	9101a021 	add	x1, x1, #0x68
  4007b0:	cb000021 	sub	x1, x1, x0
  4007b4:	9343fc21 	asr	x1, x1, #3
  4007b8:	8b41fc21 	add	x1, x1, x1, lsr #63
  4007bc:	9341fc21 	asr	x1, x1, #1
  4007c0:	b40000a1 	cbz	x1, 4007d4 <register_tm_clones+0x34>
  4007c4:	b0000002 	adrp	x2, 401000 <__libc_csu_init+0x38>
  4007c8:	f9403842 	ldr	x2, [x2, #112]
  4007cc:	b4000042 	cbz	x2, 4007d4 <register_tm_clones+0x34>
  4007d0:	d61f0040 	br	x2
  4007d4:	d65f03c0 	ret

00000000004007d8 <__do_global_dtors_aux>:
  4007d8:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  4007dc:	910003fd 	mov	x29, sp
  4007e0:	f9000bf3 	str	x19, [sp, #16]
  4007e4:	d0000093 	adrp	x19, 412000 <memcpy@GLIBC_2.17>
  4007e8:	3941a260 	ldrb	w0, [x19, #104]
  4007ec:	35000080 	cbnz	w0, 4007fc <__do_global_dtors_aux+0x24>
  4007f0:	97ffffe0 	bl	400770 <deregister_tm_clones>
  4007f4:	52800020 	mov	w0, #0x1                   	// #1
  4007f8:	3901a260 	strb	w0, [x19, #104]
  4007fc:	f9400bf3 	ldr	x19, [sp, #16]
  400800:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400804:	d65f03c0 	ret

0000000000400808 <frame_dummy>:
  400808:	17ffffe6 	b	4007a0 <register_tm_clones>

000000000040080c <init>:
  40080c:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400810:	910003fd 	mov	x29, sp
  400814:	f9000fa0 	str	x0, [x29, #24]
  400818:	b90017a1 	str	w1, [x29, #20]
  40081c:	b9002fbf 	str	wzr, [x29, #44]
  400820:	b98017a1 	ldrsw	x1, [x29, #20]
  400824:	aa0103e0 	mov	x0, x1
  400828:	d37cec00 	lsl	x0, x0, #4
  40082c:	8b010000 	add	x0, x0, x1
  400830:	d379e000 	lsl	x0, x0, #7
  400834:	97ffff97 	bl	400690 <malloc@plt>
  400838:	aa0003e1 	mov	x1, x0
  40083c:	f9400fa0 	ldr	x0, [x29, #24]
  400840:	f9000001 	str	x1, [x0]
  400844:	f9400fa0 	ldr	x0, [x29, #24]
  400848:	f9400000 	ldr	x0, [x0]
  40084c:	f100001f 	cmp	x0, #0x0
  400850:	540000c1 	b.ne	400868 <init+0x5c>  // b.any
  400854:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400858:	9101e000 	add	x0, x0, #0x78
  40085c:	97ffffa1 	bl	4006e0 <puts@plt>
  400860:	52800000 	mov	w0, #0x0                   	// #0
  400864:	97ffff87 	bl	400680 <exit@plt>
  400868:	b9002fbf 	str	wzr, [x29, #44]
  40086c:	1400001b 	b	4008d8 <init+0xcc>
  400870:	f9400fa0 	ldr	x0, [x29, #24]
  400874:	f9400002 	ldr	x2, [x0]
  400878:	b9802fa1 	ldrsw	x1, [x29, #44]
  40087c:	aa0103e0 	mov	x0, x1
  400880:	d37cec00 	lsl	x0, x0, #4
  400884:	8b010000 	add	x0, x0, x1
  400888:	d379e000 	lsl	x0, x0, #7
  40088c:	8b000040 	add	x0, x2, x0
  400890:	d2801002 	mov	x2, #0x80                  	// #128
  400894:	52800001 	mov	w1, #0x0                   	// #0
  400898:	97ffff86 	bl	4006b0 <memset@plt>
  40089c:	f9400fa0 	ldr	x0, [x29, #24]
  4008a0:	f9400002 	ldr	x2, [x0]
  4008a4:	b9802fa1 	ldrsw	x1, [x29, #44]
  4008a8:	aa0103e0 	mov	x0, x1
  4008ac:	d37cec00 	lsl	x0, x0, #4
  4008b0:	8b010000 	add	x0, x0, x1
  4008b4:	d379e000 	lsl	x0, x0, #7
  4008b8:	8b000040 	add	x0, x2, x0
  4008bc:	91020000 	add	x0, x0, #0x80
  4008c0:	d2810002 	mov	x2, #0x800                 	// #2048
  4008c4:	52800001 	mov	w1, #0x0                   	// #0
  4008c8:	97ffff7a 	bl	4006b0 <memset@plt>
  4008cc:	b9402fa0 	ldr	w0, [x29, #44]
  4008d0:	11000400 	add	w0, w0, #0x1
  4008d4:	b9002fa0 	str	w0, [x29, #44]
  4008d8:	b9402fa1 	ldr	w1, [x29, #44]
  4008dc:	b94017a0 	ldr	w0, [x29, #20]
  4008e0:	6b00003f 	cmp	w1, w0
  4008e4:	54fffc6b 	b.lt	400870 <init+0x64>  // b.tstop
  4008e8:	f9400fa0 	ldr	x0, [x29, #24]
  4008ec:	b94017a1 	ldr	w1, [x29, #20]
  4008f0:	b9001001 	str	w1, [x0, #16]
  4008f4:	f9400fa0 	ldr	x0, [x29, #24]
  4008f8:	b9000c1f 	str	wzr, [x0, #12]
  4008fc:	f9400fa0 	ldr	x0, [x29, #24]
  400900:	b9400c01 	ldr	w1, [x0, #12]
  400904:	f9400fa0 	ldr	x0, [x29, #24]
  400908:	b9000801 	str	w1, [x0, #8]
  40090c:	f9400fa0 	ldr	x0, [x29, #24]
  400910:	b900141f 	str	wzr, [x0, #20]
  400914:	d503201f 	nop
  400918:	a8c37bfd 	ldp	x29, x30, [sp], #48
  40091c:	d65f03c0 	ret

0000000000400920 <empty>:
  400920:	d10043ff 	sub	sp, sp, #0x10
  400924:	f90007e0 	str	x0, [sp, #8]
  400928:	f94007e0 	ldr	x0, [sp, #8]
  40092c:	b9400801 	ldr	w1, [x0, #8]
  400930:	f94007e0 	ldr	x0, [sp, #8]
  400934:	b9400c00 	ldr	w0, [x0, #12]
  400938:	6b00003f 	cmp	w1, w0
  40093c:	54000061 	b.ne	400948 <empty+0x28>  // b.any
  400940:	52800020 	mov	w0, #0x1                   	// #1
  400944:	14000002 	b	40094c <empty+0x2c>
  400948:	52800000 	mov	w0, #0x0                   	// #0
  40094c:	910043ff 	add	sp, sp, #0x10
  400950:	d65f03c0 	ret

0000000000400954 <full>:
  400954:	d10043ff 	sub	sp, sp, #0x10
  400958:	f90007e0 	str	x0, [sp, #8]
  40095c:	f94007e0 	ldr	x0, [sp, #8]
  400960:	b9400802 	ldr	w2, [x0, #8]
  400964:	f94007e0 	ldr	x0, [sp, #8]
  400968:	b9400c00 	ldr	w0, [x0, #12]
  40096c:	11000400 	add	w0, w0, #0x1
  400970:	f94007e1 	ldr	x1, [sp, #8]
  400974:	b9401021 	ldr	w1, [x1, #16]
  400978:	1ac10c03 	sdiv	w3, w0, w1
  40097c:	1b017c61 	mul	w1, w3, w1
  400980:	4b010000 	sub	w0, w0, w1
  400984:	6b00005f 	cmp	w2, w0
  400988:	54000061 	b.ne	400994 <full+0x40>  // b.any
  40098c:	52800020 	mov	w0, #0x1                   	// #1
  400990:	14000002 	b	400998 <full+0x44>
  400994:	52800000 	mov	w0, #0x0                   	// #0
  400998:	910043ff 	add	sp, sp, #0x10
  40099c:	d65f03c0 	ret

00000000004009a0 <enqueue>:
  4009a0:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  4009a4:	910003fd 	mov	x29, sp
  4009a8:	a90153f3 	stp	x19, x20, [sp, #16]
  4009ac:	f90017a0 	str	x0, [x29, #40]
  4009b0:	f90013a1 	str	x1, [x29, #32]
  4009b4:	f94017a0 	ldr	x0, [x29, #40]
  4009b8:	97ffffe7 	bl	400954 <full>
  4009bc:	7100001f 	cmp	w0, #0x0
  4009c0:	540000a0 	b.eq	4009d4 <enqueue+0x34>  // b.none
  4009c4:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  4009c8:	91024000 	add	x0, x0, #0x90
  4009cc:	97ffff45 	bl	4006e0 <puts@plt>
  4009d0:	14000036 	b	400aa8 <enqueue+0x108>
  4009d4:	f94017a0 	ldr	x0, [x29, #40]
  4009d8:	f9400002 	ldr	x2, [x0]
  4009dc:	f94017a0 	ldr	x0, [x29, #40]
  4009e0:	b9400c00 	ldr	w0, [x0, #12]
  4009e4:	93407c01 	sxtw	x1, w0
  4009e8:	aa0103e0 	mov	x0, x1
  4009ec:	d37cec00 	lsl	x0, x0, #4
  4009f0:	8b010000 	add	x0, x0, x1
  4009f4:	d379e000 	lsl	x0, x0, #7
  4009f8:	8b000040 	add	x0, x2, x0
  4009fc:	aa0003f4 	mov	x20, x0
  400a00:	f94013b3 	ldr	x19, [x29, #32]
  400a04:	f94013a0 	ldr	x0, [x29, #32]
  400a08:	97ffff1a 	bl	400670 <strlen@plt>
  400a0c:	aa0003e2 	mov	x2, x0
  400a10:	aa1303e1 	mov	x1, x19
  400a14:	aa1403e0 	mov	x0, x20
  400a18:	97ffff12 	bl	400660 <memcpy@plt>
  400a1c:	f94017a0 	ldr	x0, [x29, #40]
  400a20:	f9400002 	ldr	x2, [x0]
  400a24:	f94017a0 	ldr	x0, [x29, #40]
  400a28:	b9400c00 	ldr	w0, [x0, #12]
  400a2c:	93407c01 	sxtw	x1, w0
  400a30:	aa0103e0 	mov	x0, x1
  400a34:	d37cec00 	lsl	x0, x0, #4
  400a38:	8b010000 	add	x0, x0, x1
  400a3c:	d379e000 	lsl	x0, x0, #7
  400a40:	8b000040 	add	x0, x2, x0
  400a44:	91020013 	add	x19, x0, #0x80
  400a48:	f94013a0 	ldr	x0, [x29, #32]
  400a4c:	91020014 	add	x20, x0, #0x80
  400a50:	f94013a0 	ldr	x0, [x29, #32]
  400a54:	91020000 	add	x0, x0, #0x80
  400a58:	97ffff06 	bl	400670 <strlen@plt>
  400a5c:	aa0003e2 	mov	x2, x0
  400a60:	aa1403e1 	mov	x1, x20
  400a64:	aa1303e0 	mov	x0, x19
  400a68:	97fffefe 	bl	400660 <memcpy@plt>
  400a6c:	f94017a0 	ldr	x0, [x29, #40]
  400a70:	b9400c00 	ldr	w0, [x0, #12]
  400a74:	11000400 	add	w0, w0, #0x1
  400a78:	f94017a1 	ldr	x1, [x29, #40]
  400a7c:	b9401021 	ldr	w1, [x1, #16]
  400a80:	1ac10c02 	sdiv	w2, w0, w1
  400a84:	1b017c41 	mul	w1, w2, w1
  400a88:	4b010001 	sub	w1, w0, w1
  400a8c:	f94017a0 	ldr	x0, [x29, #40]
  400a90:	b9000c01 	str	w1, [x0, #12]
  400a94:	f94017a0 	ldr	x0, [x29, #40]
  400a98:	b9401400 	ldr	w0, [x0, #20]
  400a9c:	11000401 	add	w1, w0, #0x1
  400aa0:	f94017a0 	ldr	x0, [x29, #40]
  400aa4:	b9001401 	str	w1, [x0, #20]
  400aa8:	a94153f3 	ldp	x19, x20, [sp, #16]
  400aac:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400ab0:	d65f03c0 	ret

0000000000400ab4 <dequeue>:
  400ab4:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400ab8:	910003fd 	mov	x29, sp
  400abc:	f9000fa0 	str	x0, [x29, #24]
  400ac0:	f9000ba1 	str	x1, [x29, #16]
  400ac4:	f9400fa0 	ldr	x0, [x29, #24]
  400ac8:	97ffff96 	bl	400920 <empty>
  400acc:	7100001f 	cmp	w0, #0x0
  400ad0:	540000a0 	b.eq	400ae4 <dequeue+0x30>  // b.none
  400ad4:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400ad8:	91028000 	add	x0, x0, #0xa0
  400adc:	97ffff01 	bl	4006e0 <puts@plt>
  400ae0:	1400004b 	b	400c0c <dequeue+0x158>
  400ae4:	f9400ba3 	ldr	x3, [x29, #16]
  400ae8:	f9400fa0 	ldr	x0, [x29, #24]
  400aec:	f9400002 	ldr	x2, [x0]
  400af0:	f9400fa0 	ldr	x0, [x29, #24]
  400af4:	b9400800 	ldr	w0, [x0, #8]
  400af8:	93407c01 	sxtw	x1, w0
  400afc:	aa0103e0 	mov	x0, x1
  400b00:	d37cec00 	lsl	x0, x0, #4
  400b04:	8b010000 	add	x0, x0, x1
  400b08:	d379e000 	lsl	x0, x0, #7
  400b0c:	8b000040 	add	x0, x2, x0
  400b10:	d2801002 	mov	x2, #0x80                  	// #128
  400b14:	aa0003e1 	mov	x1, x0
  400b18:	aa0303e0 	mov	x0, x3
  400b1c:	97fffed1 	bl	400660 <memcpy@plt>
  400b20:	f9400ba0 	ldr	x0, [x29, #16]
  400b24:	91020003 	add	x3, x0, #0x80
  400b28:	f9400fa0 	ldr	x0, [x29, #24]
  400b2c:	f9400002 	ldr	x2, [x0]
  400b30:	f9400fa0 	ldr	x0, [x29, #24]
  400b34:	b9400800 	ldr	w0, [x0, #8]
  400b38:	93407c01 	sxtw	x1, w0
  400b3c:	aa0103e0 	mov	x0, x1
  400b40:	d37cec00 	lsl	x0, x0, #4
  400b44:	8b010000 	add	x0, x0, x1
  400b48:	d379e000 	lsl	x0, x0, #7
  400b4c:	8b000040 	add	x0, x2, x0
  400b50:	91020000 	add	x0, x0, #0x80
  400b54:	d2810002 	mov	x2, #0x800                 	// #2048
  400b58:	aa0003e1 	mov	x1, x0
  400b5c:	aa0303e0 	mov	x0, x3
  400b60:	97fffec0 	bl	400660 <memcpy@plt>
  400b64:	f9400fa0 	ldr	x0, [x29, #24]
  400b68:	f9400002 	ldr	x2, [x0]
  400b6c:	f9400fa0 	ldr	x0, [x29, #24]
  400b70:	b9400800 	ldr	w0, [x0, #8]
  400b74:	93407c01 	sxtw	x1, w0
  400b78:	aa0103e0 	mov	x0, x1
  400b7c:	d37cec00 	lsl	x0, x0, #4
  400b80:	8b010000 	add	x0, x0, x1
  400b84:	d379e000 	lsl	x0, x0, #7
  400b88:	8b000040 	add	x0, x2, x0
  400b8c:	d2801002 	mov	x2, #0x80                  	// #128
  400b90:	52800001 	mov	w1, #0x0                   	// #0
  400b94:	97fffec7 	bl	4006b0 <memset@plt>
  400b98:	f9400fa0 	ldr	x0, [x29, #24]
  400b9c:	f9400002 	ldr	x2, [x0]
  400ba0:	f9400fa0 	ldr	x0, [x29, #24]
  400ba4:	b9400800 	ldr	w0, [x0, #8]
  400ba8:	93407c01 	sxtw	x1, w0
  400bac:	aa0103e0 	mov	x0, x1
  400bb0:	d37cec00 	lsl	x0, x0, #4
  400bb4:	8b010000 	add	x0, x0, x1
  400bb8:	d379e000 	lsl	x0, x0, #7
  400bbc:	8b000040 	add	x0, x2, x0
  400bc0:	91020000 	add	x0, x0, #0x80
  400bc4:	d2810002 	mov	x2, #0x800                 	// #2048
  400bc8:	52800001 	mov	w1, #0x0                   	// #0
  400bcc:	97fffeb9 	bl	4006b0 <memset@plt>
  400bd0:	f9400fa0 	ldr	x0, [x29, #24]
  400bd4:	b9400800 	ldr	w0, [x0, #8]
  400bd8:	11000400 	add	w0, w0, #0x1
  400bdc:	f9400fa1 	ldr	x1, [x29, #24]
  400be0:	b9401021 	ldr	w1, [x1, #16]
  400be4:	1ac10c02 	sdiv	w2, w0, w1
  400be8:	1b017c41 	mul	w1, w2, w1
  400bec:	4b010001 	sub	w1, w0, w1
  400bf0:	f9400fa0 	ldr	x0, [x29, #24]
  400bf4:	b9000801 	str	w1, [x0, #8]
  400bf8:	f9400fa0 	ldr	x0, [x29, #24]
  400bfc:	b9401400 	ldr	w0, [x0, #20]
  400c00:	51000401 	sub	w1, w0, #0x1
  400c04:	f9400fa0 	ldr	x0, [x29, #24]
  400c08:	b9001401 	str	w1, [x0, #20]
  400c0c:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400c10:	d65f03c0 	ret

0000000000400c14 <display>:
  400c14:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400c18:	910003fd 	mov	x29, sp
  400c1c:	f9000fa0 	str	x0, [x29, #24]
  400c20:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400c24:	9102c000 	add	x0, x0, #0xb0
  400c28:	97fffeae 	bl	4006e0 <puts@plt>
  400c2c:	f9400fa0 	ldr	x0, [x29, #24]
  400c30:	b9400800 	ldr	w0, [x0, #8]
  400c34:	b9002fa0 	str	w0, [x29, #44]
  400c38:	1400001d 	b	400cac <display+0x98>
  400c3c:	f9400fa0 	ldr	x0, [x29, #24]
  400c40:	f9400002 	ldr	x2, [x0]
  400c44:	b9802fa1 	ldrsw	x1, [x29, #44]
  400c48:	aa0103e0 	mov	x0, x1
  400c4c:	d37cec00 	lsl	x0, x0, #4
  400c50:	8b010000 	add	x0, x0, x1
  400c54:	d379e000 	lsl	x0, x0, #7
  400c58:	8b000040 	add	x0, x2, x0
  400c5c:	aa0003e5 	mov	x5, x0
  400c60:	f9400fa0 	ldr	x0, [x29, #24]
  400c64:	f9400002 	ldr	x2, [x0]
  400c68:	b9802fa1 	ldrsw	x1, [x29, #44]
  400c6c:	aa0103e0 	mov	x0, x1
  400c70:	d37cec00 	lsl	x0, x0, #4
  400c74:	8b010000 	add	x0, x0, x1
  400c78:	d379e000 	lsl	x0, x0, #7
  400c7c:	8b000040 	add	x0, x2, x0
  400c80:	91020001 	add	x1, x0, #0x80
  400c84:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400c88:	91036000 	add	x0, x0, #0xd8
  400c8c:	aa0103e4 	mov	x4, x1
  400c90:	b9402fa3 	ldr	w3, [x29, #44]
  400c94:	aa0503e2 	mov	x2, x5
  400c98:	b9402fa1 	ldr	w1, [x29, #44]
  400c9c:	97fffe99 	bl	400700 <printf@plt>
  400ca0:	b9402fa0 	ldr	w0, [x29, #44]
  400ca4:	11000400 	add	w0, w0, #0x1
  400ca8:	b9002fa0 	str	w0, [x29, #44]
  400cac:	f9400fa0 	ldr	x0, [x29, #24]
  400cb0:	b9401000 	ldr	w0, [x0, #16]
  400cb4:	b9402fa1 	ldr	w1, [x29, #44]
  400cb8:	6b00003f 	cmp	w1, w0
  400cbc:	54fffc0b 	b.lt	400c3c <display+0x28>  // b.tstop
  400cc0:	d503201f 	nop
  400cc4:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400cc8:	d65f03c0 	ret

0000000000400ccc <display_all>:
  400ccc:	a9bd7bfd 	stp	x29, x30, [sp, #-48]!
  400cd0:	910003fd 	mov	x29, sp
  400cd4:	f9000fa0 	str	x0, [x29, #24]
  400cd8:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400cdc:	9103e000 	add	x0, x0, #0xf8
  400ce0:	97fffe80 	bl	4006e0 <puts@plt>
  400ce4:	b9002fbf 	str	wzr, [x29, #44]
  400ce8:	1400001d 	b	400d5c <display_all+0x90>
  400cec:	f9400fa0 	ldr	x0, [x29, #24]
  400cf0:	f9400002 	ldr	x2, [x0]
  400cf4:	b9802fa1 	ldrsw	x1, [x29, #44]
  400cf8:	aa0103e0 	mov	x0, x1
  400cfc:	d37cec00 	lsl	x0, x0, #4
  400d00:	8b010000 	add	x0, x0, x1
  400d04:	d379e000 	lsl	x0, x0, #7
  400d08:	8b000040 	add	x0, x2, x0
  400d0c:	aa0003e5 	mov	x5, x0
  400d10:	f9400fa0 	ldr	x0, [x29, #24]
  400d14:	f9400002 	ldr	x2, [x0]
  400d18:	b9802fa1 	ldrsw	x1, [x29, #44]
  400d1c:	aa0103e0 	mov	x0, x1
  400d20:	d37cec00 	lsl	x0, x0, #4
  400d24:	8b010000 	add	x0, x0, x1
  400d28:	d379e000 	lsl	x0, x0, #7
  400d2c:	8b000040 	add	x0, x2, x0
  400d30:	91020001 	add	x1, x0, #0x80
  400d34:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400d38:	91036000 	add	x0, x0, #0xd8
  400d3c:	aa0103e4 	mov	x4, x1
  400d40:	b9402fa3 	ldr	w3, [x29, #44]
  400d44:	aa0503e2 	mov	x2, x5
  400d48:	b9402fa1 	ldr	w1, [x29, #44]
  400d4c:	97fffe6d 	bl	400700 <printf@plt>
  400d50:	b9402fa0 	ldr	w0, [x29, #44]
  400d54:	11000400 	add	w0, w0, #0x1
  400d58:	b9002fa0 	str	w0, [x29, #44]
  400d5c:	f9400fa0 	ldr	x0, [x29, #24]
  400d60:	b9401000 	ldr	w0, [x0, #16]
  400d64:	b9402fa1 	ldr	w1, [x29, #44]
  400d68:	6b00003f 	cmp	w1, w0
  400d6c:	54fffc0b 	b.lt	400cec <display_all+0x20>  // b.tstop
  400d70:	d503201f 	nop
  400d74:	a8c37bfd 	ldp	x29, x30, [sp], #48
  400d78:	d65f03c0 	ret

0000000000400d7c <clean>:
  400d7c:	a9be7bfd 	stp	x29, x30, [sp, #-32]!
  400d80:	910003fd 	mov	x29, sp
  400d84:	f9000fa0 	str	x0, [x29, #24]
  400d88:	f9400fa0 	ldr	x0, [x29, #24]
  400d8c:	f9400000 	ldr	x0, [x0]
  400d90:	f100001f 	cmp	x0, #0x0
  400d94:	54000180 	b.eq	400dc4 <clean+0x48>  // b.none
  400d98:	f9400fa0 	ldr	x0, [x29, #24]
  400d9c:	f9400000 	ldr	x0, [x0]
  400da0:	97fffe54 	bl	4006f0 <free@plt>
  400da4:	f9400fa0 	ldr	x0, [x29, #24]
  400da8:	f900001f 	str	xzr, [x0]
  400dac:	f9400fa0 	ldr	x0, [x29, #24]
  400db0:	b900081f 	str	wzr, [x0, #8]
  400db4:	f9400fa0 	ldr	x0, [x29, #24]
  400db8:	b9000c1f 	str	wzr, [x0, #12]
  400dbc:	f9400fa0 	ldr	x0, [x29, #24]
  400dc0:	b900101f 	str	wzr, [x0, #16]
  400dc4:	d503201f 	nop
  400dc8:	a8c27bfd 	ldp	x29, x30, [sp], #32
  400dcc:	d65f03c0 	ret

0000000000400dd0 <main>:
  400dd0:	d2844610 	mov	x16, #0x2230                	// #8752
  400dd4:	cb3063ff 	sub	sp, sp, x16
  400dd8:	a9007bfd 	stp	x29, x30, [sp]
  400ddc:	910003fd 	mov	x29, sp
  400de0:	910043a0 	add	x0, x29, #0x10
  400de4:	d2844001 	mov	x1, #0x2200                	// #8704
  400de8:	aa0103e2 	mov	x2, x1
  400dec:	52800001 	mov	w1, #0x0                   	// #0
  400df0:	97fffe30 	bl	4006b0 <memset@plt>
  400df4:	52800140 	mov	w0, #0xa                   	// #10
  400df8:	b9222fa0 	str	w0, [x29, #8748]
  400dfc:	910043a2 	add	x2, x29, #0x10
  400e00:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400e04:	91048001 	add	x1, x0, #0x120
  400e08:	aa0203e0 	mov	x0, x2
  400e0c:	a9400c22 	ldp	x2, x3, [x1]
  400e10:	a9000c02 	stp	x2, x3, [x0]
  400e14:	a9410c22 	ldp	x2, x3, [x1, #16]
  400e18:	a9010c02 	stp	x2, x3, [x0, #16]
  400e1c:	79404021 	ldrh	w1, [x1, #32]
  400e20:	79004001 	strh	w1, [x0, #32]
  400e24:	910043a0 	add	x0, x29, #0x10
  400e28:	91020002 	add	x2, x0, #0x80
  400e2c:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400e30:	91052001 	add	x1, x0, #0x148
  400e34:	aa0203e0 	mov	x0, x2
  400e38:	a9400c22 	ldp	x2, x3, [x1]
  400e3c:	a9000c02 	stp	x2, x3, [x0]
  400e40:	a9410c22 	ldp	x2, x3, [x1, #16]
  400e44:	a9010c02 	stp	x2, x3, [x0, #16]
  400e48:	79404021 	ldrh	w1, [x1, #32]
  400e4c:	79004001 	strh	w1, [x0, #32]
  400e50:	910043a0 	add	x0, x29, #0x10
  400e54:	91220002 	add	x2, x0, #0x880
  400e58:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400e5c:	91048001 	add	x1, x0, #0x120
  400e60:	aa0203e0 	mov	x0, x2
  400e64:	a9400c22 	ldp	x2, x3, [x1]
  400e68:	a9000c02 	stp	x2, x3, [x0]
  400e6c:	a9410c22 	ldp	x2, x3, [x1, #16]
  400e70:	a9010c02 	stp	x2, x3, [x0, #16]
  400e74:	79404021 	ldrh	w1, [x1, #32]
  400e78:	79004001 	strh	w1, [x0, #32]
  400e7c:	910043a0 	add	x0, x29, #0x10
  400e80:	91240002 	add	x2, x0, #0x900
  400e84:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400e88:	91052001 	add	x1, x0, #0x148
  400e8c:	aa0203e0 	mov	x0, x2
  400e90:	a9400c22 	ldp	x2, x3, [x1]
  400e94:	a9000c02 	stp	x2, x3, [x0]
  400e98:	a9410c22 	ldp	x2, x3, [x1, #16]
  400e9c:	a9010c02 	stp	x2, x3, [x0, #16]
  400ea0:	79404021 	ldrh	w1, [x1, #32]
  400ea4:	79004001 	strh	w1, [x0, #32]
  400ea8:	910043a1 	add	x1, x29, #0x10
  400eac:	d2822000 	mov	x0, #0x1100                	// #4352
  400eb0:	8b000022 	add	x2, x1, x0
  400eb4:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400eb8:	91048001 	add	x1, x0, #0x120
  400ebc:	aa0203e0 	mov	x0, x2
  400ec0:	a9400c22 	ldp	x2, x3, [x1]
  400ec4:	a9000c02 	stp	x2, x3, [x0]
  400ec8:	a9410c22 	ldp	x2, x3, [x1, #16]
  400ecc:	a9010c02 	stp	x2, x3, [x0, #16]
  400ed0:	79404021 	ldrh	w1, [x1, #32]
  400ed4:	79004001 	strh	w1, [x0, #32]
  400ed8:	910043a1 	add	x1, x29, #0x10
  400edc:	d2823000 	mov	x0, #0x1180                	// #4480
  400ee0:	8b000022 	add	x2, x1, x0
  400ee4:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400ee8:	91052001 	add	x1, x0, #0x148
  400eec:	aa0203e0 	mov	x0, x2
  400ef0:	a9400c22 	ldp	x2, x3, [x1]
  400ef4:	a9000c02 	stp	x2, x3, [x0]
  400ef8:	a9410c22 	ldp	x2, x3, [x1, #16]
  400efc:	a9010c02 	stp	x2, x3, [x0, #16]
  400f00:	79404021 	ldrh	w1, [x1, #32]
  400f04:	79004001 	strh	w1, [x0, #32]
  400f08:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f0c:	91084000 	add	x0, x0, #0x210
  400f10:	b9622fa1 	ldr	w1, [x29, #8748]
  400f14:	97fffe3e 	bl	40080c <init>
  400f18:	910043a1 	add	x1, x29, #0x10
  400f1c:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f20:	91084000 	add	x0, x0, #0x210
  400f24:	97fffe9f 	bl	4009a0 <enqueue>
  400f28:	910043a0 	add	x0, x29, #0x10
  400f2c:	91220001 	add	x1, x0, #0x880
  400f30:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f34:	91084000 	add	x0, x0, #0x210
  400f38:	97fffe9a 	bl	4009a0 <enqueue>
  400f3c:	910043a0 	add	x0, x29, #0x10
  400f40:	91220001 	add	x1, x0, #0x880
  400f44:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f48:	91084000 	add	x0, x0, #0x210
  400f4c:	97fffe95 	bl	4009a0 <enqueue>
  400f50:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f54:	91084000 	add	x0, x0, #0x210
  400f58:	97ffff2f 	bl	400c14 <display>
  400f5c:	910043a1 	add	x1, x29, #0x10
  400f60:	d2833000 	mov	x0, #0x1980                	// #6528
  400f64:	8b000021 	add	x1, x1, x0
  400f68:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f6c:	91084000 	add	x0, x0, #0x210
  400f70:	97fffed1 	bl	400ab4 <dequeue>
  400f74:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400f78:	91084000 	add	x0, x0, #0x210
  400f7c:	97ffff54 	bl	400ccc <display_all>
  400f80:	910043a1 	add	x1, x29, #0x10
  400f84:	d2834000 	mov	x0, #0x1a00                	// #6656
  400f88:	8b000022 	add	x2, x1, x0
  400f8c:	910043a1 	add	x1, x29, #0x10
  400f90:	d2833000 	mov	x0, #0x1980                	// #6528
  400f94:	8b000021 	add	x1, x1, x0
  400f98:	b0000000 	adrp	x0, 401000 <__libc_csu_init+0x38>
  400f9c:	9105c000 	add	x0, x0, #0x170
  400fa0:	97fffdd8 	bl	400700 <printf@plt>
  400fa4:	91400ba0 	add	x0, x29, #0x2, lsl #12
  400fa8:	91084000 	add	x0, x0, #0x210
  400fac:	97ffff74 	bl	400d7c <clean>
  400fb0:	52800000 	mov	w0, #0x0                   	// #0
  400fb4:	a9407bfd 	ldp	x29, x30, [sp]
  400fb8:	d2844610 	mov	x16, #0x2230                	// #8752
  400fbc:	8b3063ff 	add	sp, sp, x16
  400fc0:	d65f03c0 	ret
  400fc4:	00000000 	.inst	0x00000000 ; undefined

0000000000400fc8 <__libc_csu_init>:
  400fc8:	a9bc7bfd 	stp	x29, x30, [sp, #-64]!
  400fcc:	910003fd 	mov	x29, sp
  400fd0:	a901d7f4 	stp	x20, x21, [sp, #24]
  400fd4:	b0000094 	adrp	x20, 411000 <__FRAME_END__+0xfe78>
  400fd8:	b0000095 	adrp	x21, 411000 <__FRAME_END__+0xfe78>
  400fdc:	91374294 	add	x20, x20, #0xdd0
  400fe0:	913722b5 	add	x21, x21, #0xdc8
  400fe4:	a902dff6 	stp	x22, x23, [sp, #40]
  400fe8:	cb150294 	sub	x20, x20, x21
  400fec:	f9001ff8 	str	x24, [sp, #56]
  400ff0:	2a0003f6 	mov	w22, w0
  400ff4:	aa0103f7 	mov	x23, x1
  400ff8:	9343fe94 	asr	x20, x20, #3
  400ffc:	aa0203f8 	mov	x24, x2
  401000:	97fffd8a 	bl	400628 <_init>
  401004:	b4000194 	cbz	x20, 401034 <__libc_csu_init+0x6c>
  401008:	f9000bb3 	str	x19, [x29, #16]
  40100c:	d2800013 	mov	x19, #0x0                   	// #0
  401010:	f8737aa3 	ldr	x3, [x21, x19, lsl #3]
  401014:	aa1803e2 	mov	x2, x24
  401018:	aa1703e1 	mov	x1, x23
  40101c:	2a1603e0 	mov	w0, w22
  401020:	91000673 	add	x19, x19, #0x1
  401024:	d63f0060 	blr	x3
  401028:	eb13029f 	cmp	x20, x19
  40102c:	54ffff21 	b.ne	401010 <__libc_csu_init+0x48>  // b.any
  401030:	f9400bb3 	ldr	x19, [x29, #16]
  401034:	a941d7f4 	ldp	x20, x21, [sp, #24]
  401038:	a942dff6 	ldp	x22, x23, [sp, #40]
  40103c:	f9401ff8 	ldr	x24, [sp, #56]
  401040:	a8c47bfd 	ldp	x29, x30, [sp], #64
  401044:	d65f03c0 	ret

0000000000401048 <__libc_csu_fini>:
  401048:	d65f03c0 	ret

Disassembly of section .fini:

000000000040104c <_fini>:
  40104c:	a9bf7bfd 	stp	x29, x30, [sp, #-16]!
  401050:	910003fd 	mov	x29, sp
  401054:	a8c17bfd 	ldp	x29, x30, [sp], #16
  401058:	d65f03c0 	ret
